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This commit is contained in:
Enrico Fraccaroli
2021-10-26 08:24:50 +02:00
parent 7a78333bae
commit 60a56e1139
9 changed files with 166 additions and 109 deletions
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mentos/inc/descriptor_tables/gdt.h
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/// @brief Data structures concerning the Global Descriptor Table (GDT).
/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
/// See LICENSE.md for details.
/// @addtogroup descriptor_tables Memory Management Modules
/// @brief GDT, IDT and TSS are all data structures specified by Intel x86
/// architecture in memory management module.
mentos/inc/descriptor_tables/idt.h
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/// @brief Data structures concerning the Interrupt Descriptor Table (IDT).
/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
/// See LICENSE.md for details.
/// @addtogroup descriptor_tables Descriptor Tables
/// @{
/// @addtogroup idt Interrupt Descriptor Table (IDT)
mentos/inc/descriptor_tables/isr.h
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/// @brief Data structures concerning the Interrupt Service Routines (ISRs).
/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
/// See LICENSE.md for details.
/// @addtogroup descriptor_tables Descriptor Tables
/// @{
/// @addtogroup isr Interrupt Service Routines (ISRs)
mentos/inc/descriptor_tables/tss.h
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/// @brief Data structures concerning the Task State Segment (TSS).
/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
/// See LICENSE.md for details.
/// @addtogroup descriptor_tables Descriptor Tables
/// @{
/// @defgroup tss Task State Segment (TSS)
mentos/inc/devices/fpu.h
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@@ -3,7 +3,12 @@
/// @brief Floating Point Unit (FPU).
/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
/// See LICENSE.md for details.
/// @addtogroup devices Hardware Interfaces
/// @brief Data structures and functions for managing hardware devices.
/// @{
/// @addtogroup fpu Floating Point Unit (FPU)
/// @brief Device designed to carry out operations on floating-point numbers.
/// @{
#pragma once
#include "stdint.h"
@@ -124,3 +129,6 @@ void unswitch_fpu();
/// @brief Enable the FPU context handling.
/// @return 0 if fails, 1 if succeed.
int fpu_install();
/// @}
/// @}
mentos/inc/devices/pci.h
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@@ -3,13 +3,18 @@
/// @brief Routines for interfacing with the Peripheral Component Interconnect (PCI).
/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
/// See LICENSE.md for details.
///! @cond Doxygen_Suppress
/// @addtogroup devices Hardware Interfaces
/// @{
/// @addtogroup pci Peripheral Component Interconnect (PCI)
/// @brief Routines for interfacing with the peripherals.
/// @{
#pragma once
#include "stdint.h"
/// @defgroup pci_configuration_space The PCI configuration space.
/// @name PCI Configuration Space
/// @brief
/// The PCI Specification defines the organization of the 256-byte.
/// Configuration Space registers and imposes a specific template for the
/// space. Figures 2 & 3 show the layout of the 256-byte Configuration space.
@@ -19,65 +24,98 @@
/// functionality.
/// @{
/// 16 bits - Identifies the manufacturer of the device. Where valid IDs are
/// allocated by PCI-SIG (the list is here) to ensure uniqueness and 0xFFFF is
/// an invalid value that will be returned on read accesses to Configuration
/// Space registers of non-existent devices.
/// @brief Identifies the manufacturer of the device (16 bits). Where valid IDs are allocated by PCI-SIG (the list is here) to
/// ensure uniqueness and 0xFFFF is an invalid value that will be returned
/// on read accesses to Configuration Space registers of non-existent devices.
#define PCI_VENDOR_ID 0x00
/// 16 bits - Identifies the particular device. Where valid IDs are allocated
/// by the vendor.
/// @brief Identifies the particular device (16 bits).
#define PCI_DEVICE_ID 0x02
/// 16 bits - Provides control over a device's ability to generate and
/// respond to PCI cycles. Where the only functionality guaranteed to be
/// supported by all devices is, when a 0 is written to this register, the
/// device is disconnected from the PCI bus for all accesses except
/// Configuration Space access.
/// @brief Provides control over a device's ability to generate and
/// respond to PCI cycles (16 bits). Where the only functionality guaranteed to be supported by all
/// devices is, when a 0 is written to this register, the device is disconnected
/// from the PCI bus for all accesses except Configuration Space access.
#define PCI_COMMAND 0x04
/// 16 bits - A register used to record status information for PCI bus
/// related events.
/// @brief A register used to record status information for PCI bus related events (16 bits).
#define PCI_STATUS 0x06
/// 8 bits - Specifies a revision identifier for a particular device. Where
/// valid IDs are allocated by the vendor.
/// @brief Specifies a revision identifier for a particular device (8 bits).
#define PCI_REVISION_ID 0x08
/// 8 bits - A read-only register that specifies a register-level
/// programming interface the device has, if it has any at all.
/// @brief A read-only register that specifies a register-level
/// programming interface the device has, if it has any at all (8 bits).
#define PCI_PROG_IF 0x09
/// 8 bits - A read-only register that specifies the specific function the
/// device performs.
/// @brief A read-only register that specifies the specific function the
/// device performs (8 bits).
#define PCI_SUBCLASS 0x0a
/// 8 bits - A read-only register that specifies the type of function the
/// device performs.
/// @brief A read-only register that specifies the type of function the
/// device performs (8 bits).
#define PCI_CLASS 0x0b
/// 8 bits - Specifies the system cache line size in 32-bit units. A device
/// @brief Specifies the system cache line size in 32-bit units (8 bits). A device
/// can limit the number of cacheline sizes it can support, if a unsupported
/// value is written to this field, the device will behave as if a value of 0
/// was written.
#define PCI_CACHE_LINE_SIZE 0x0c
/// 8 bits - Specifies the latency timer in units of PCI bus clocks.
/// Specifies the latency timer in units of PCI bus clocks (8 bits).
#define PCI_LATENCY_TIMER 0x0d
/// 8 bits - Identifies the layout of the rest of the header beginning at
/// byte 0x10 of the header and also specifies whether or not the device has
/// multiple functions. Where a value of 0x00 specifies a general device, a
/// value of 0x01 specifies a PCI-to-PCI bridge, and a value of 0x02 specifies
/// a CardBus bridge. If bit 7 of this register is set, the device has
/// multiple functions; otherwise, it is a single function device.
/// @brief Identifies the layout of the header based on the type of device it
/// begins at byte 0x10 of the header (8 bits). A value of 0x00 specifies a general device, a value of 0x01 specifies
/// a PCI-to-PCI bridge, and a value of 0x02 specifies a CardBus bridge.
/// If bit 7 of this register is set, the device has multiple functions;
/// otherwise, it is a single function device.
#define PCI_HEADER_TYPE 0x0e
/// 8 bits - Represents that status and allows control of a devices BIST
/// (built-in self test).
/// @brief Represents that status and allows control of devices built-in self tests (8 bits).
#define PCI_BIST 0x0f
/// @defgroup pci_base_addresses The PCI base addresses.
/// @brief Points to the Card Information Structure and is used by devices that share silicon
/// between CardBus and PCI.
#define PCI_CARDBUS_CIS 0x28
/// @brief Points to the Subsystem Vendor ID
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
/// @brief Points to the Subsystem Device ID
#define PCI_SUBSYSTEM_ID 0x2e
/// @brief Bits 31..11 are address, 10..1 reserved
#define PCI_ROM_ADDRESS 0x30
/// @brief Points to a linked list of new capabilities implemented by the device. Used if bit 4 of the status register (Capabilities List bit) is set to 1.
/// The bottom two bits are reserved and should be masked before the Pointer
/// is used to access the Configuration Space.
#define PCI_CAPABILITY_LIST 0x34
/// @brief Specifies which input of the system interrupt controllers the device's
/// interrupt pin is connected to and is implemented by any device that makes
/// use of an interrupt pin. For the x86 architecture this register
/// corresponds to the PIC IRQ numbers 0-15 (and not I/O APIC IRQ numbers) and
/// a value of 0xFF defines no connection.
#define PCI_INTERRUPT_LINE 0x3c
/// @brief Specifies which interrupt pin the device uses. Where a value of 0x01 is INTA#, 0x02 is INTB#, 0x03 is INTC#,
/// 0x04 is INTD#, and 0x00 means the device does not use an interrupt pin.
#define PCI_INTERRUPT_PIN 0x3d
/// @brief A read-only register that specifies the burst period length, in 1/4
/// microsecond units, that the device needs (assuming a 33 MHz clock rate).
#define PCI_MIN_GNT 0x3e
/// @brief A read-only register that specifies how often the device needs access to
/// the PCI bus (in 1/4 microsecond units).
#define PCI_MAX_LAT 0x3f
/// @}
/// @name PCI Base Addresses
/// @brief
/// Base addresses specify locations in memory or I/O space.
/// Decoded size can be determined by writing a value of 0xffffffff to the
/// register, and reading it back. Only 1 bits are decoded.
@@ -90,40 +128,7 @@
#define PCI_BASE_ADDRESS_4 0x20 ///< Location of base address 4.
#define PCI_BASE_ADDRESS_5 0x24 ///< Location of base address 5.
/// @} pci_base_addresses
/// Points to the Card Information Structure and is used by devices that
/// share silicon between CardBus and PCI.
#define PCI_CARDBUS_CIS 0x28
/// Points to the Subsystem Vendor ID
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
/// Points to the Subsystem Device ID
#define PCI_SUBSYSTEM_ID 0x2e
/// Bits 31..11 are address, 10..1 reserved
#define PCI_ROM_ADDRESS 0x30
/// Points to a linked list of new capabilities implemented by the device.
/// Used if bit 4 of the status register (Capabilities List bit) is set to 1.
/// The bottom two bits are reserved and should be masked before the Pointer
/// is used to access the Configuration Space.
#define PCI_CAPABILITY_LIST 0x34
/// Specifies which input of the system interrupt controllers the device's
/// interrupt pin is connected to and is implemented by any device that makes
/// use of an interrupt pin. For the x86 architecture this register
/// corresponds to the PIC IRQ numbers 0-15 (and not I/O APIC IRQ numbers) and
/// a value of 0xFF defines no connection.
#define PCI_INTERRUPT_LINE 0x3c
/// Specifies which interrupt pin the device uses. Where a value of 0x01 is
/// INTA#, 0x02 is INTB#, 0x03 is INTC#, 0x04 is INTD#, and 0x00 means the
/// device does not use an interrupt pin.
#define PCI_INTERRUPT_PIN 0x3d
/// A read-only register that specifies the burst period length, in 1/4
/// microsecond units, that the device needs (assuming a 33 MHz clock rate).
#define PCI_MIN_GNT 0x3e
/// A read-only register that specifies how often the device needs access to
/// the PCI bus (in 1/4 microsecond units).
#define PCI_MAX_LAT 0x3f
/// @} pci_configuration_space
/// @}
#define PCI_PRIMARY_BUS 0x18 ///< Primary bus number.
#define PCI_SECONDARY_BUS 0x19 ///< Secondary bus number.
@@ -225,4 +230,5 @@ int pci_get_interrupt(uint32_t device);
/// @brief
void pci_debug_scan();
///! @endcond
/// @}
/// @}
mentos/inc/drivers/rtc.h
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/// @brief Real Time Clock (RTC) driver.
/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
/// See LICENSE.md for details.
/// @addtogroup drivers Device Drivers
/// @{
/// @addtogroup rtc Real Time Clock (RTC)
/// @brief Routines for interfacing with the real-time clock.
/// @{
#pragma once
@@ -13,4 +18,6 @@
extern void gettime(tm_t *time);
/// @brief Installs the Real Time Clock.
extern void rtc_install(void);
extern void rtc_install(void);
/// @}