Improve comments.
This commit is contained in:
Enrico Fraccaroli
+28
-14
@@ -1,5 +1,8 @@
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/* The following are overrides over hard-coded styles in Doxygen */
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.sm-dox {
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@@ -28,7 +31,10 @@ table,
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/* Moz */
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@@ -471,7 +482,7 @@ table.memberdecls {
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.mdescLeft,
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@@ -554,7 +565,7 @@ table.memberdecls {
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@@ -716,7 +727,7 @@ div.directory {
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background-color: #728DC1;
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@@ -762,7 +773,10 @@ div.directory {
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div.dynheader {
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@@ -929,7 +943,7 @@ table.classindex {
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@@ -1269,7 +1283,7 @@ div.toc li.level4 {
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+46
-20
@@ -7,11 +7,26 @@ $cyan-color: #56b6c2;
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$yellow-color: #e5c07b;
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$code-font: monaco,
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Consolas,
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"Lucida Console",
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monospace;
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/* font families */
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$page-font-family: Roboto,
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Lucida,
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sans-serif;
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$code-font-family: Consolas,
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monospace,
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fixed;
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/* font sizes */
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$title-font-size: 22px;
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/* colors */
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$title-fg-color: $white-color;
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$title-bg-color: $black-color;
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$menu-bg-color: $gutter-color;
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@@ -69,7 +84,10 @@ table,
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div,
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p,
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dl {
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font: 400 14px/22px Roboto, sans-serif;
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font-size: $page-font-size;
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font-family: $page-font-family;
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font-weight: 400;
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display: block;
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margin-block-start: 0em;
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margin-block-end: 0em;
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@@ -89,7 +107,10 @@ ul {
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p.reference,
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p.definition {
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font: 400 14px/22px Roboto, sans-serif;
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font-size: $page-font-size;
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font-family: $page-font-family;
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font-weight: 400;
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}
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@@ -100,7 +121,10 @@ h1.groupheader {
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}
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.title {
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font: 400 14px/28px Roboto, sans-serif;
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font-size: $page-font-size;
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font-family: $page-font-family;
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font-weight: 400;
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font-size: 150%;
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font-weight: bold;
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margin: 10px 2px;
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@@ -326,7 +350,7 @@ pre.fragment {
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overflow: auto;
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word-wrap: break-word;
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@@ -341,10 +365,9 @@ div.fragment {
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}
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div.line {
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text-wrap: unrestricted;
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white-space: -moz-pre-wrap;
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/* Moz */
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@@ -651,7 +674,7 @@ table.memberdecls {
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.memItemLeft,
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.memItemRight {
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font-family: $code-font;
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.mdescLeft,
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}
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.memname {
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}
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@@ -1023,8 +1046,8 @@ div.directory {
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font-family: Arial, Helvetica;
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font-weight: bold;
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font-size: 12px;
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height: 14px;
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display: inline-block;
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background-color: #728DC1;
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color: white;
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@@ -1074,7 +1097,10 @@ div.directory {
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}
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table.directory {
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font: 400 14px Roboto, sans-serif;
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font-weight: 400;
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}
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@@ -1272,7 +1298,7 @@ table.classindex {
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}
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div.ingroups {
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font-size: 8pt;
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font-size: 10pt;
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width: 50%;
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text-align: left;
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}
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@@ -1686,7 +1712,7 @@ tr.heading h2 {
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#powerTip div {
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margin: 0px;
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padding: 0px;
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font: 12px/16px Roboto, sans-serif;
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font: 12px/16px $page-font-family;
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}
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#powerTip:before,
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@@ -3,7 +3,6 @@
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/// @brief Data structures concerning the Global Descriptor Table (GDT).
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/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
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/// See LICENSE.md for details.
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/// @addtogroup descriptor_tables Memory Management Modules
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/// @brief GDT, IDT and TSS are all data structures specified by Intel x86
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/// architecture in memory management module.
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@@ -3,7 +3,6 @@
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/// @brief Data structures concerning the Interrupt Descriptor Table (IDT).
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/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
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/// See LICENSE.md for details.
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/// @addtogroup descriptor_tables Descriptor Tables
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/// @{
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/// @addtogroup idt Interrupt Descriptor Table (IDT)
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@@ -3,7 +3,6 @@
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/// @brief Data structures concerning the Interrupt Service Routines (ISRs).
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/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
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/// See LICENSE.md for details.
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/// @addtogroup descriptor_tables Descriptor Tables
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/// @{
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/// @addtogroup isr Interrupt Service Routines (ISRs)
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@@ -3,7 +3,6 @@
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/// @brief Data structures concerning the Task State Segment (TSS).
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/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
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/// See LICENSE.md for details.
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/// @addtogroup descriptor_tables Descriptor Tables
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/// @{
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/// @defgroup tss Task State Segment (TSS)
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@@ -3,7 +3,12 @@
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/// @brief Floating Point Unit (FPU).
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/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
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/// See LICENSE.md for details.
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/// @addtogroup devices Hardware Interfaces
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/// @brief Data structures and functions for managing hardware devices.
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/// @{
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/// @addtogroup fpu Floating Point Unit (FPU)
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/// @brief Device designed to carry out operations on floating-point numbers.
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/// @{
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#pragma once
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#include "stdint.h"
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@@ -124,3 +129,6 @@ void unswitch_fpu();
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/// @brief Enable the FPU context handling.
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/// @return 0 if fails, 1 if succeed.
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int fpu_install();
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/// @}
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/// @}
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+75
-69
@@ -3,13 +3,18 @@
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/// @brief Routines for interfacing with the Peripheral Component Interconnect (PCI).
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/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
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/// See LICENSE.md for details.
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///! @cond Doxygen_Suppress
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/// @addtogroup devices Hardware Interfaces
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/// @{
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/// @addtogroup pci Peripheral Component Interconnect (PCI)
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/// @brief Routines for interfacing with the peripherals.
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/// @{
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#pragma once
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#include "stdint.h"
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/// @defgroup pci_configuration_space The PCI configuration space.
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/// @name PCI Configuration Space
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/// @brief
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/// The PCI Specification defines the organization of the 256-byte.
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/// Configuration Space registers and imposes a specific template for the
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/// space. Figures 2 & 3 show the layout of the 256-byte Configuration space.
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@@ -19,65 +24,98 @@
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/// functionality.
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/// @{
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/// 16 bits - Identifies the manufacturer of the device. Where valid IDs are
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/// allocated by PCI-SIG (the list is here) to ensure uniqueness and 0xFFFF is
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/// an invalid value that will be returned on read accesses to Configuration
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/// Space registers of non-existent devices.
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/// @brief Identifies the manufacturer of the device (16 bits). Where valid IDs are allocated by PCI-SIG (the list is here) to
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/// ensure uniqueness and 0xFFFF is an invalid value that will be returned
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/// on read accesses to Configuration Space registers of non-existent devices.
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#define PCI_VENDOR_ID 0x00
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/// 16 bits - Identifies the particular device. Where valid IDs are allocated
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/// by the vendor.
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/// @brief Identifies the particular device (16 bits).
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#define PCI_DEVICE_ID 0x02
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/// 16 bits - Provides control over a device's ability to generate and
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/// respond to PCI cycles. Where the only functionality guaranteed to be
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/// supported by all devices is, when a 0 is written to this register, the
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/// device is disconnected from the PCI bus for all accesses except
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/// Configuration Space access.
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/// @brief Provides control over a device's ability to generate and
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/// respond to PCI cycles (16 bits). Where the only functionality guaranteed to be supported by all
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/// devices is, when a 0 is written to this register, the device is disconnected
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/// from the PCI bus for all accesses except Configuration Space access.
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#define PCI_COMMAND 0x04
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/// 16 bits - A register used to record status information for PCI bus
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/// related events.
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/// @brief A register used to record status information for PCI bus related events (16 bits).
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#define PCI_STATUS 0x06
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/// 8 bits - Specifies a revision identifier for a particular device. Where
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/// valid IDs are allocated by the vendor.
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/// @brief Specifies a revision identifier for a particular device (8 bits).
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#define PCI_REVISION_ID 0x08
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/// 8 bits - A read-only register that specifies a register-level
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/// programming interface the device has, if it has any at all.
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||||
/// @brief A read-only register that specifies a register-level
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||||
/// programming interface the device has, if it has any at all (8 bits).
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#define PCI_PROG_IF 0x09
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/// 8 bits - A read-only register that specifies the specific function the
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||||
/// device performs.
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||||
/// @brief A read-only register that specifies the specific function the
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/// device performs (8 bits).
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#define PCI_SUBCLASS 0x0a
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||||
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||||
/// 8 bits - A read-only register that specifies the type of function the
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||||
/// device performs.
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||||
/// @brief A read-only register that specifies the type of function the
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||||
/// device performs (8 bits).
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||||
#define PCI_CLASS 0x0b
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||||
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||||
/// 8 bits - Specifies the system cache line size in 32-bit units. A device
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||||
/// @brief Specifies the system cache line size in 32-bit units (8 bits). A device
|
||||
/// can limit the number of cacheline sizes it can support, if a unsupported
|
||||
/// value is written to this field, the device will behave as if a value of 0
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||||
/// was written.
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||||
#define PCI_CACHE_LINE_SIZE 0x0c
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||||
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||||
/// 8 bits - Specifies the latency timer in units of PCI bus clocks.
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||||
/// Specifies the latency timer in units of PCI bus clocks (8 bits).
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||||
#define PCI_LATENCY_TIMER 0x0d
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||||
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||||
/// 8 bits - Identifies the layout of the rest of the header beginning at
|
||||
/// byte 0x10 of the header and also specifies whether or not the device has
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||||
/// multiple functions. Where a value of 0x00 specifies a general device, a
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||||
/// value of 0x01 specifies a PCI-to-PCI bridge, and a value of 0x02 specifies
|
||||
/// a CardBus bridge. If bit 7 of this register is set, the device has
|
||||
/// multiple functions; otherwise, it is a single function device.
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||||
/// @brief Identifies the layout of the header based on the type of device it
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||||
/// begins at byte 0x10 of the header (8 bits). A value of 0x00 specifies a general device, a value of 0x01 specifies
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||||
/// a PCI-to-PCI bridge, and a value of 0x02 specifies a CardBus bridge.
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||||
/// If bit 7 of this register is set, the device has multiple functions;
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||||
/// otherwise, it is a single function device.
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||||
#define PCI_HEADER_TYPE 0x0e
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||||
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||||
/// 8 bits - Represents that status and allows control of a devices BIST
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||||
/// (built-in self test).
|
||||
/// @brief Represents that status and allows control of devices built-in self tests (8 bits).
|
||||
#define PCI_BIST 0x0f
|
||||
|
||||
/// @defgroup pci_base_addresses The PCI base addresses.
|
||||
/// @brief Points to the Card Information Structure and is used by devices that share silicon
|
||||
/// between CardBus and PCI.
|
||||
#define PCI_CARDBUS_CIS 0x28
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||||
|
||||
/// @brief Points to the Subsystem Vendor ID
|
||||
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
|
||||
|
||||
/// @brief Points to the Subsystem Device ID
|
||||
#define PCI_SUBSYSTEM_ID 0x2e
|
||||
|
||||
/// @brief Bits 31..11 are address, 10..1 reserved
|
||||
#define PCI_ROM_ADDRESS 0x30
|
||||
|
||||
/// @brief Points to a linked list of new capabilities implemented by the device. Used if bit 4 of the status register (Capabilities List bit) is set to 1.
|
||||
/// The bottom two bits are reserved and should be masked before the Pointer
|
||||
/// is used to access the Configuration Space.
|
||||
#define PCI_CAPABILITY_LIST 0x34
|
||||
|
||||
/// @brief Specifies which input of the system interrupt controllers the device's
|
||||
/// interrupt pin is connected to and is implemented by any device that makes
|
||||
/// use of an interrupt pin. For the x86 architecture this register
|
||||
/// corresponds to the PIC IRQ numbers 0-15 (and not I/O APIC IRQ numbers) and
|
||||
/// a value of 0xFF defines no connection.
|
||||
#define PCI_INTERRUPT_LINE 0x3c
|
||||
|
||||
/// @brief Specifies which interrupt pin the device uses. Where a value of 0x01 is INTA#, 0x02 is INTB#, 0x03 is INTC#,
|
||||
/// 0x04 is INTD#, and 0x00 means the device does not use an interrupt pin.
|
||||
#define PCI_INTERRUPT_PIN 0x3d
|
||||
|
||||
/// @brief A read-only register that specifies the burst period length, in 1/4
|
||||
/// microsecond units, that the device needs (assuming a 33 MHz clock rate).
|
||||
#define PCI_MIN_GNT 0x3e
|
||||
|
||||
/// @brief A read-only register that specifies how often the device needs access to
|
||||
/// the PCI bus (in 1/4 microsecond units).
|
||||
#define PCI_MAX_LAT 0x3f
|
||||
|
||||
/// @}
|
||||
|
||||
/// @name PCI Base Addresses
|
||||
/// @brief
|
||||
/// Base addresses specify locations in memory or I/O space.
|
||||
/// Decoded size can be determined by writing a value of 0xffffffff to the
|
||||
/// register, and reading it back. Only 1 bits are decoded.
|
||||
@@ -90,40 +128,7 @@
|
||||
#define PCI_BASE_ADDRESS_4 0x20 ///< Location of base address 4.
|
||||
#define PCI_BASE_ADDRESS_5 0x24 ///< Location of base address 5.
|
||||
|
||||
/// @} pci_base_addresses
|
||||
|
||||
/// Points to the Card Information Structure and is used by devices that
|
||||
/// share silicon between CardBus and PCI.
|
||||
#define PCI_CARDBUS_CIS 0x28
|
||||
/// Points to the Subsystem Vendor ID
|
||||
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
|
||||
/// Points to the Subsystem Device ID
|
||||
#define PCI_SUBSYSTEM_ID 0x2e
|
||||
/// Bits 31..11 are address, 10..1 reserved
|
||||
#define PCI_ROM_ADDRESS 0x30
|
||||
/// Points to a linked list of new capabilities implemented by the device.
|
||||
/// Used if bit 4 of the status register (Capabilities List bit) is set to 1.
|
||||
/// The bottom two bits are reserved and should be masked before the Pointer
|
||||
/// is used to access the Configuration Space.
|
||||
#define PCI_CAPABILITY_LIST 0x34
|
||||
/// Specifies which input of the system interrupt controllers the device's
|
||||
/// interrupt pin is connected to and is implemented by any device that makes
|
||||
/// use of an interrupt pin. For the x86 architecture this register
|
||||
/// corresponds to the PIC IRQ numbers 0-15 (and not I/O APIC IRQ numbers) and
|
||||
/// a value of 0xFF defines no connection.
|
||||
#define PCI_INTERRUPT_LINE 0x3c
|
||||
/// Specifies which interrupt pin the device uses. Where a value of 0x01 is
|
||||
/// INTA#, 0x02 is INTB#, 0x03 is INTC#, 0x04 is INTD#, and 0x00 means the
|
||||
/// device does not use an interrupt pin.
|
||||
#define PCI_INTERRUPT_PIN 0x3d
|
||||
/// A read-only register that specifies the burst period length, in 1/4
|
||||
/// microsecond units, that the device needs (assuming a 33 MHz clock rate).
|
||||
#define PCI_MIN_GNT 0x3e
|
||||
/// A read-only register that specifies how often the device needs access to
|
||||
/// the PCI bus (in 1/4 microsecond units).
|
||||
#define PCI_MAX_LAT 0x3f
|
||||
|
||||
/// @} pci_configuration_space
|
||||
/// @}
|
||||
|
||||
#define PCI_PRIMARY_BUS 0x18 ///< Primary bus number.
|
||||
#define PCI_SECONDARY_BUS 0x19 ///< Secondary bus number.
|
||||
@@ -225,4 +230,5 @@ int pci_get_interrupt(uint32_t device);
|
||||
/// @brief
|
||||
void pci_debug_scan();
|
||||
|
||||
///! @endcond
|
||||
/// @}
|
||||
/// @}
|
||||
@@ -3,6 +3,11 @@
|
||||
/// @brief Real Time Clock (RTC) driver.
|
||||
/// @copyright (c) 2014-2021 This file is distributed under the MIT License.
|
||||
/// See LICENSE.md for details.
|
||||
/// @addtogroup drivers Device Drivers
|
||||
/// @{
|
||||
/// @addtogroup rtc Real Time Clock (RTC)
|
||||
/// @brief Routines for interfacing with the real-time clock.
|
||||
/// @{
|
||||
|
||||
#pragma once
|
||||
|
||||
@@ -13,4 +18,6 @@
|
||||
extern void gettime(tm_t *time);
|
||||
|
||||
/// @brief Installs the Real Time Clock.
|
||||
extern void rtc_install(void);
|
||||
extern void rtc_install(void);
|
||||
|
||||
/// @}
|
||||
Reference in New Issue
Block a user