Fix ATA read/write and test it.

CMakeLists.txt

@@ -138,6 +138,7 @@ elseif(${DEBUGGING_TYPE} STREQUAL DEBUG_STDIO)
 endif(${DEBUGGING_TYPE} STREQUAL DEBUG_LOG)
 set(EMULATOR_FLAGS ${EMULATOR_FLAGS} -vga std)
 set(EMULATOR_FLAGS ${EMULATOR_FLAGS} -m ${MEMORY_SIZE})
+set(EMULATOR_FLAGS ${EMULATOR_FLAGS} -drive file=rootfs.img,format=raw)
 set(EMULATOR_KERNEL -kernel mentos/kernel-bootloader.bin)
 set(EMULATOR_FS -initrd initrd)
 

mentos/inc/devices/pci.h

@@ -13,6 +13,90 @@
 
 #include "stdint.h"
 
+typedef enum {
+    /// @brief If set to 1 the device can respond to I/O Space accesses;
+    /// otherwise, the device's response is disabled.
+    pci_command_io_space = 0,
+    /// @brief If set to 1 the device can respond to Memory Space accesses;
+    /// otherwise, the device's response is disabled.
+    pci_command_memory_space = 1,
+    /// @brief If set to 1 the device can behave as a bus master; otherwise, the
+    /// device can not generate PCI accesses.
+    pci_command_bus_master = 2,
+    /// @brief If set to 1 the device can monitor Special Cycle operations;
+    /// otherwise, the device will ignore them.
+    pci_command_special_cycles = 3,
+    /// @brief If set to 1 the device can generate the Memory Write and
+    /// Invalidate command; otherwise, the Memory Write command must be used.
+    pci_command_mw_ie = 4,
+    /// @brief If set to 1 the device does not respond to palette register
+    /// writes and will snoop the data; otherwise, the device will trate palette
+    /// write accesses like all other accesses.
+    pci_command_vga_palette_snoop = 5,
+    /// @brief If set to 1 the device will take its normal action when a parity
+    /// error is detected; otherwise, when an error is detected, the device will
+    /// set bit 15 of the Status register (Detected Parity Error Status Bit),
+    /// but will not assert the PERR# (Parity Error) pin and will continue
+    /// operation as normal.
+    pci_command_parity_error_response = 6,
+    /// @brief If set to 1 the SERR# driver is enabled; otherwise, the driver is
+    /// disabled.
+    pci_command_serr_enable = 8,
+    /// @brief If set to 1 indicates a device is allowed to generate fast
+    /// back-to-back transactions; otherwise, fast back-to-back transactions are
+    /// only allowed to the same agent.
+    pci_command_fast_bb_enable = 9,
+    /// @brief If set to 1 the assertion of the devices INTx# signal is
+    /// disabled; otherwise, assertion of the signal is enabled.
+    pci_command_interrupt_disable = 10,
+} pci_command_bit_t;
+
+typedef enum {
+    /// @brief Represents the state of the device's INTx# signal. If set to 1
+    /// and bit 10 of the Command register (Interrupt Disable bit) is set to 0
+    /// the signal will be asserted; otherwise, the signal will be ignored.
+    pci_status_interrupt_status = 3,
+    /// @brief If set to 1 the device implements the pointer for a New
+    /// Capabilities Linked list at offset 0x34; otherwise, the linked list is
+    /// not available.
+    pci_status_capabilities_list = 4,
+    /// @brief If set to 1 the device is capable of running at 66 MHz;
+    /// otherwise, the device runs at 33 MHz.
+    pci_status_66_MHz_capable = 5,
+    /// @brief If set to 1 the device can accept fast back-to-back transactions
+    /// that are not from the same agent; otherwise, transactions can only be
+    /// accepted from the same agent.
+    pci_status_fast_bb_capable = 7,
+    /// @brief This bit is only set when the following conditions are met. The
+    /// bus agent asserted PERR# on a read or observed an assertion of PERR# on
+    /// a write, the agent setting the bit acted as the bus master for the
+    /// operation in which the error occurred, and bit 6 of the Command register
+    /// (Parity Error Response bit) is set to 1.
+    pci_status_master_data_parity_error = 8,
+    /// @brief Read only bits that represent the slowest time that a device will
+    /// assert DEVSEL# for any bus command except Configuration Space read and
+    /// writes. Where a value of 0x0 represents fast timing, a value of 0x1
+    /// represents medium timing, and a value of 0x2 represents slow timing.
+    pci_status_devsel_timing_low = 9,
+    /// @brief The second bit required to set the devsel.
+    pci_status_devsel_timing_high = 10,
+    /// @brief This bit will be set to 1 whenever a target device terminates a
+    /// transaction with Target-Abort.
+    pci_status_signalled_target_abort = 11,
+    /// @brief This bit will be set to 1, by a master device, whenever its
+    /// transaction is terminated with Target-Abort.
+    pci_status_received_target_abort = 12,
+    /// @brief This bit will be set to 1, by a master device, whenever its
+    /// transaction (except for Special Cycle transactions) is terminated with
+    /// Master-Abort.
+    pci_status_received_master_abort = 13,
+    /// @brief This bit will be set to 1 whenever the device asserts SERR#.
+    pci_status_signalled_system_error = 14,
+    /// @brief This bit will be set to 1 whenever the device detects a parity
+    /// error, even if parity error handling is disabled.
+    pci_status_detected_parity_error = 15,
+} pci_status_bit_t;
+
 /// @name PCI Configuration Space
 /// @brief
 /// The PCI Specification defines the organization of the 256-byte.
@@ -25,7 +109,7 @@
 /// @{
 
 /// @brief Identifies the manufacturer of the device (16 bits). Where valid IDs are allocated by PCI-SIG (the list is here) to
-/// ensure uniqueness and 0xFFFF is an invalid value that will be returned 
+/// ensure uniqueness and 0xFFFF is an invalid value that will be returned
 /// on read accesses to Configuration Space registers of non-existent devices.
 #define PCI_VENDOR_ID 0x00
 
@@ -33,7 +117,7 @@
 #define PCI_DEVICE_ID 0x02
 
 /// @brief Provides control over a device's ability to generate and
-/// respond to PCI cycles (16 bits). Where the only functionality guaranteed to be supported by all 
+/// respond to PCI cycles (16 bits). Where the only functionality guaranteed to be supported by all
 /// devices is, when a 0 is written to this register, the device is disconnected
 /// from the PCI bus for all accesses except Configuration Space access.
 #define PCI_COMMAND 0x04
@@ -65,10 +149,10 @@
 /// Specifies the latency timer in units of PCI bus clocks (8 bits).
 #define PCI_LATENCY_TIMER 0x0d
 
-/// @brief Identifies the layout of the header based on the type of device it 
+/// @brief Identifies the layout of the header based on the type of device it
 /// begins at byte 0x10 of the header (8 bits). A value of 0x00 specifies a general device, a value of 0x01 specifies
-/// a PCI-to-PCI bridge, and a value of 0x02 specifies a CardBus bridge. 
-/// If bit 7 of this register is set, the device has multiple functions; 
+/// a PCI-to-PCI bridge, and a value of 0x02 specifies a CardBus bridge.
+/// If bit 7 of this register is set, the device has multiple functions;
 /// otherwise, it is a single function device.
 #define PCI_HEADER_TYPE 0x0e
 
@@ -100,7 +184,7 @@
 /// a value of 0xFF defines no connection.
 #define PCI_INTERRUPT_LINE 0x3c
 
-/// @brief Specifies which interrupt pin the device uses. Where a value of 0x01 is INTA#, 0x02 is INTB#, 0x03 is INTC#, 
+/// @brief Specifies which interrupt pin the device uses. Where a value of 0x01 is INTA#, 0x02 is INTB#, 0x03 is INTC#,
 /// 0x04 is INTD#, and 0x00 means the device does not use an interrupt pin.
 #define PCI_INTERRUPT_PIN 0x3d
 

mentos/src/kernel.c

@@ -261,7 +261,7 @@ int kmain(boot_info_t *boot_informations)
 
     //==========================================================================
     // Scan for ata devices.
-    if (!ata_initialize()) {
+    if (ata_initialize()) {
         print_fail();
         return 1;
     }