Enrico Fraccaroli (Galfurian)
499 lines
17 KiB
C
499 lines
17 KiB
C
/// @file pci.c
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/// @brief Routines for PCI initialization.
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/// @copyright (c) 2014-2022 This file is distributed under the MIT License.
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/// See LICENSE.md for details.
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///! @cond Doxygen_Suppress
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// Include the kernel log levels.
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#include "sys/kernel_levels.h"
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/// Change the header.
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#define __DEBUG_HEADER__ "[PCI ]"
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/// Set the log level.
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#define __DEBUG_LEVEL__ LOGLEVEL_NOTICE
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#include "devices/pci.h"
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#include "io/debug.h"
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#include "string.h"
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#include "io/port_io.h"
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void pci_write_field(uint32_t device, int field, int size, uint32_t value)
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{
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(void)size;
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outportl(PCI_ADDRESS_PORT, pci_get_addr(device, field));
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#if 0
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if (size == 4)
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outportl(PCI_VALUE_PORT, value);
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else if (size == 2)
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outports(PCI_VALUE_PORT, value);
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else if (size == 1)
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outportb(PCI_VALUE_PORT, value);
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#else
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outportl(PCI_VALUE_PORT, value);
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#endif
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}
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uint32_t pci_read_field(uint32_t device, int field, int size)
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{
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outportl(PCI_ADDRESS_PORT, pci_get_addr(device, field));
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if (size == 4) {
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return inportl(PCI_VALUE_PORT);
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} else if (size == 2) {
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return inports(PCI_VALUE_PORT + (field & 2));
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} else if (size == 1) {
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return inportb(PCI_VALUE_PORT + (field & 3));
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}
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return 0xFFFF;
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}
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uint32_t pci_find_type(uint32_t device)
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{
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return pci_read_field(device, PCI_CLASS, 1) << 16 |
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pci_read_field(device, PCI_SUBCLASS, 1) << 8 |
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pci_read_field(device, PCI_PROG_IF, 1);
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}
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struct {
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uint16_t id;
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const char *name;
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} _pci_vendors[] = {
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{ 0x1022, "AMD" },
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{ 0x106b, "Apple, Inc." },
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{ 0x1234, "Bochs/QEMU" },
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{ 0x1274, "Ensoniq" },
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{ 0x15ad, "VMWare" },
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{ 0x8086, "Intel Corporation" },
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{ 0x80EE, "VirtualBox" },
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};
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struct {
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uint16_t ven_id;
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uint16_t dev_id;
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const char *name;
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} _pci_devices[] = {
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{ 0x1022, 0x2000, "PCNet Ethernet Controller (pcnet)" },
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{ 0x106b, 0x003f, "OHCI Controller" },
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{ 0x1234, 0x1111, "VGA BIOS Graphics Extensions" },
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{ 0x1274, 0x1371, "Creative Labs CT2518 (ensoniq audio)" },
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{ 0x15ad, 0x0740, "VM Communication Interface" },
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{ 0x15ad, 0x0405, "SVGA II Adapter" },
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{ 0x15ad, 0x0790, "PCI bridge" },
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{ 0x15ad, 0x07a0, "PCI Express Root Port" },
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{ 0x8086, 0x100e, "Gigabit Ethernet Controller (e1000)" },
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{ 0x8086, 0x100f, "Gigabit Ethernet Controller (e1000)" },
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{ 0x8086, 0x1237, "PCI & Memory" },
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{ 0x8086, 0x2415, "AC'97 Audio Chipset" },
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{ 0x8086, 0x7000, "PCI-to-ISA Bridge" },
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{ 0x8086, 0x7010, "IDE Interface" },
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{ 0x8086, 0x7110, "PIIX4 ISA" },
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{ 0x8086, 0x7111, "PIIX4 IDE" },
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{ 0x8086, 0x7113, "Power Management Controller" },
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{ 0x8086, 0x7190, "Host Bridge" },
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{ 0x8086, 0x7191, "AGP Bridge" },
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{ 0x80EE, 0xBEEF, "Bochs/QEMU-compatible Graphics Adapter" },
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{ 0x80EE, 0xCAFE, "Guest Additions Device" },
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};
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struct {
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uint32_t id;
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const char *name;
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} _pci_classes[] = {
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{ 0x000000, "Legacy Device" },
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{ 0x000100, "VGA-Compatible Device" },
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{ 0x010000, "SCSI bus controller" },
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{ 0x010100, "ISA Compatibility mode-only controller" },
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{ 0x010105, "PCI native mode-only controller" },
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{ 0x01010a, "ISA Compatibility mode controller, supports both channels "
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"switched to PCI native mode" },
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{ 0x01010f, "PCI native mode controller, supports both channels switched "
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"to ISA compatibility mode" },
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{ 0x010180,
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"ISA Compatibility mode-only controller, supports bus mastering" },
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{ 0x010185, "PCI native mode-only controller, supports bus mastering" },
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{ 0x01018a, "ISA Compatibility mode controller, supports both channels "
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"switched to PCI native mode, supports bus mastering" },
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{ 0x01018f, "PCI native mode controller, supports both channels switched "
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"\to ISA compatibility mode, supports bus mastering" },
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{ 0x010200, "Floppy disk controller" },
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{ 0x010300, "IPI bus controller" },
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{ 0x010400, "RAID controller" },
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{ 0x010520, "ATA controller, single stepping" },
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{ 0x010530, "ATA controller, continuous" },
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{ 0x010600, "Serial ATA controller - vendor specific interface" },
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{ 0x010601, "Serial ATA controller - AHCI 1.0 interface" },
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{ 0x010700, "Serial Attached SCSI controller" },
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{ 0x018000, "Mass Storage controller" },
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{ 0x020000, "Ethernet controller" },
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{ 0x020100, "Token Ring controller" },
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{ 0x020200, "FDDI controller" },
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{ 0x020300, "ATM controller" },
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{ 0x020400, "ISDN controller" },
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{ 0x020500, "WorldFip controller" },
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// { 0x0206xx , "PICMG 2.14 Multi Computing" },
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{ 0x028000, "Network controller" },
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{ 0x030000, "VGA Display controller" },
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{ 0x030001, "8514-compatible Display controller" },
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{ 0x030100, "XGA Display controller" },
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{ 0x030200, "3D Display controller" },
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{ 0x038000, "Display controller" },
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{ 0x040000, "Video device" },
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{ 0x040100, "Audio device" },
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{ 0x040200, "Computer Telephony device" },
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{ 0x048000, "Multimedia device" },
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{ 0x050000, "RAM memory controller" },
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{ 0x050100, "Flash memory controller" },
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{ 0x058000, "Memory controller" },
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{ 0x060000, "Host bridge" },
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{ 0x060100, "ISA bridge" },
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{ 0x060200, "EISA bridge" },
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{ 0x060300, "MCA bridge" },
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{ 0x060400, "PCI-to-PCI bridge" },
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{ 0x060401, "PCI-to-PCI bridge (subtractive decoding)" },
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{ 0x060500, "PCMCIA bridge" },
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{ 0x060600, "NuBus bridge" },
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{ 0x060700, "CardBus bridge" },
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// { 0x0608xx , "RACEway bridge" },
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{ 0x060940, "PCI-to-PCI bridge, Semi-transparent, primary facing Host" },
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{ 0x060980, "PCI-to-PCI bridge, Semi-transparent, secondary facing Host" },
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{ 0x060A00, "InfiniBand-to-PCI host bridge" },
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{ 0x068000, "Bridge device" },
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{ 0x070000, "Generic XT-compatible serial controller" },
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{ 0x070001, "16450-compatible serial controller" },
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{ 0x070002, "16550-compatible serial controller" },
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{ 0x070003, "16650-compatible serial controller" },
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{ 0x070004, "16750-compatible serial controller" },
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{ 0x070005, "16850-compatible serial controller" },
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{ 0x070006, "16950-compatible serial controller" },
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{ 0x070100, "Parallel port" },
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{ 0x070101, "Bi-directional parallel port" },
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{ 0x070102, "ECP 1.X compliant parallel port" },
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{ 0x070103, "IEEE1284 controller" },
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{ 0x0701FE, "IEEE1284 target device" },
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{ 0x070200, "Multiport serial controller" },
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{ 0x070300, "Generic modem" },
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{ 0x070301, "Hayes 16450-compatible modem" },
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{ 0x070302, "Hayes 16550-compatible modem" },
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{ 0x070303, "Hayes 16650-compatible modem" },
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{ 0x070304, "Hayes 16750-compatible modem" },
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{ 0x070400, "GPIB (IEEE 488.1/2) controller" },
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{ 0x070500, "Smart Card" },
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{ 0x078000, "Communications device" },
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{ 0x080000, "Generic 8259 PIC" },
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{ 0x080001, "ISA PIC" },
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{ 0x080002, "EISA PIC" },
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{ 0x080010, "I/O APIC interrupt controller" },
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{ 0x080020, "I/O(x) APIC interrupt controller" },
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{ 0x080100, "Generic 8237 DMA controller" },
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{ 0x080101, "ISA DMA controller" },
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{ 0x080102, "EISA DMA controller" },
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{ 0x080200, "Generic 8254 system timer" },
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{ 0x080201, "ISA system timer" },
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{ 0x080202, "EISA system timer-pair" },
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{ 0x080300, "Generic RTC controller" },
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{ 0x080301, "ISA RTC controller" },
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{ 0x080400, "Generic PCI Hot-Plug controller" },
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{ 0x080500, "SD Host controller" },
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{ 0x088000, "System peripheral" },
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{ 0x090000, "Keyboard controller" },
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{ 0x090100, "Digitizer (pen)" },
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{ 0x090200, "Mouse controller" },
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{ 0x090300, "Scanner controller" },
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{ 0x090400, "Generic Gameport controller" },
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{ 0x090410, "Legacy Gameport controller" },
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{ 0x098000, "Input controller" },
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{ 0x0a0000, "Generic docking station" },
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{ 0x0a8000, "Docking station" },
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{ 0x0b0000, "386 Processor" },
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{ 0x0b0100, "486 Processor" },
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{ 0x0b0200, "Pentium Processor" },
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{ 0x0b1000, "Alpha Processor" },
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{ 0x0b2000, "PowerPC Processor" },
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{ 0x0b3000, "MIPS Processor" },
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{ 0x0b4000, "Co-processor" },
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{ 0x0c0000, "IEEE 1394 (FireWire)" },
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{ 0x0c0010, "IEEE 1394 -- OpenHCI spec" },
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{ 0x0c0100, "ACCESS.bus" },
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{ 0x0c0200, "SSA" },
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{ 0x0c0300, "Universal Serial Bus (UHC spec)" },
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{ 0x0c0310, "Universal Serial Bus (Open Host spec)" },
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{ 0x0c0320, "USB2 Host controller (Intel Enhanced HCI spec)" },
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{ 0x0c0380, "Universal Serial Bus (no PI spec)" },
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{ 0x0c03FE, "USB Target Device" },
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{ 0x0c0400, "Fibre Channel" },
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{ 0x0c0500, "System Management Bus" },
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{ 0x0c0600, "InfiniBand" },
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{ 0x0c0700, "IPMI SMIC Interface" },
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{ 0x0c0701, "IPMI Kybd Controller Style Interface" },
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{ 0x0c0702, "IPMI Block Transfer Interface" },
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// { 0x0c08xx , "SERCOS Interface" },
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{ 0x0c0900, "CANbus" },
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{ 0x0d100, "iRDA compatible controller" },
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{ 0x0d100, "Consumer IR controller" },
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{ 0x0d100, "RF controller" },
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{ 0x0d100, "Bluetooth controller" },
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{ 0x0d100, "Broadband controller" },
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{ 0x0d100, "Ethernet (802.11a 5 GHz) controller" },
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{ 0x0d100, "Ethernet (802.11b 2.4 GHz) controller" },
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{ 0x0d100, "Wireless controller" },
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// { 0x0e00xx , "I2O Intelligent I/O, spec 1.0" },
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{ 0x0e0000, "Message FIFO at offset 040h" },
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{ 0x0f0100, "TV satellite comm. controller" },
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{ 0x0f0200, "Audio satellite comm. controller" },
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{ 0x0f0300, "Voice satellite comm. controller" },
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{ 0x0f0400, "Data satellite comm. controller" },
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{ 0x100000, "Network and computing en/decryption" },
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{ 0x101000, "Entertainment en/decryption" },
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{ 0x108000, "En/Decryption" },
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{ 0x110000, "DPIO modules" },
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{ 0x110100, "Perf. counters" },
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{ 0x111000, "Comm. synch., time and freq. test" },
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{ 0x112000, "Management card" },
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{ 0x118000, "Data acq./Signal proc." },
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};
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const char *pci_vendor_lookup(unsigned short vendor_id)
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{
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for (int i = 0; i < sizeof(_pci_vendors) / sizeof(_pci_vendors[0]); ++i) {
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if (_pci_vendors[i].id == vendor_id) {
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return _pci_vendors[i].name;
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}
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}
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return "Unknown";
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}
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const char *pci_device_lookup(unsigned short vendor_id, unsigned short device_id)
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{
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for (int i = 0; i < sizeof(_pci_devices) / sizeof(_pci_devices[0]); ++i) {
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if (_pci_devices[i].ven_id == vendor_id &&
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_pci_devices[i].dev_id == device_id) {
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return _pci_devices[i].name;
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}
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}
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return "Unknown";
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}
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const char *pci_class_lookup(uint32_t class_code)
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{
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for (int i = 0; i < sizeof(_pci_classes) / sizeof(_pci_classes[0]); ++i) {
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if (_pci_classes[i].id == class_code) {
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return _pci_classes[i].name;
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}
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}
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return "Unknown";
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}
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void pci_scan_hit(pci_scan_func_t f, uint32_t device, void *extra)
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{
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uint16_t vendor_id = (uint16_t)pci_read_field(device, PCI_VENDOR_ID, 2);
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uint16_t device_id = (uint16_t)pci_read_field(device, PCI_DEVICE_ID, 2);
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f(device, vendor_id, device_id, extra);
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}
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void pci_scan_func(pci_scan_func_t f, int type, int bus, int slot, int func, void *extra)
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{
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uint32_t device = pci_box_device(bus, slot, func);
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if ((type == -1) || (type == pci_find_type(device))) {
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pci_scan_hit(f, device, extra);
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}
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if (pci_find_type(device) == PCI_TYPE_BRIDGE) {
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pci_scan_bus(f, type, pci_read_field(device, PCI_SECONDARY_BUS, 1), extra);
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}
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}
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void pci_scan_slot(pci_scan_func_t f, int type, int bus, int slot, void *extra)
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{
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uint32_t device = pci_box_device(bus, slot, 0);
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if (pci_read_field(device, PCI_VENDOR_ID, 2) == PCI_NONE) {
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return;
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}
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pci_scan_func(f, type, bus, slot, 0, extra);
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if (!pci_read_field(device, PCI_HEADER_TYPE, 1)) {
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return;
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}
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for (int func = 1; func < 8; func++) {
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device = pci_box_device(bus, slot, func);
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if (pci_read_field(device, PCI_VENDOR_ID, 2) != PCI_NONE) {
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pci_scan_func(f, type, bus, slot, func, extra);
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}
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}
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}
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void pci_scan_bus(pci_scan_func_t f, int type, int bus, void *extra)
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{
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for (int slot = 0; slot < 32; ++slot) {
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pci_scan_slot(f, type, bus, slot, extra);
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}
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}
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void pci_scan(pci_scan_func_t f, int type, void *extra)
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{
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if ((pci_read_field(0, PCI_HEADER_TYPE, 1) & 0x80) == 0) {
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pci_scan_bus(f, type, 0, extra);
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return;
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}
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for (int func = 0; func < 8; ++func) {
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uint32_t device = pci_box_device(0, 0, func);
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if (pci_read_field(device, PCI_VENDOR_ID, 2) == PCI_NONE) {
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break;
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}
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pci_scan_bus(f, type, func, extra);
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}
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}
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static void find_isa_bridge(uint32_t device, uint16_t vendorid, uint16_t deviceid, void *extra)
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{
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if (vendorid == 0x8086 && (deviceid == 0x7000 || deviceid == 0x7110)) {
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*((uint32_t *)extra) = device;
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}
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}
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static uint32_t pci_isa = 0;
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static uint32_t pci_remaps[4] = { 0 };
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void pci_remap()
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{
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pci_scan(&find_isa_bridge, -1, &pci_isa);
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if (pci_isa) {
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pr_default("PCI-to-ISA interrupt mappings by line:\n");
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for (int i = 0; i < 4; ++i) {
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pci_remaps[i] = pci_read_field(pci_isa, 0x60 + i, 1);
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pr_default("\tLine %d: 0x%2x\n", i + 1, pci_remaps[i]);
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}
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uint32_t out = 0;
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memcpy(&out, &pci_remaps, 4);
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pci_write_field(pci_isa, 0x60, 4, out);
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}
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}
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int pci_get_interrupt(uint32_t device)
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{
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if (pci_isa == 0) {
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return pci_read_field(device, PCI_INTERRUPT_LINE, 1);
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}
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uint32_t irq_pin = pci_read_field(device, PCI_INTERRUPT_PIN, 1);
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if (irq_pin == 0) {
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pr_default("PCI device does not specific interrupt line\n");
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return pci_read_field(device, PCI_INTERRUPT_LINE, 1);
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}
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int pirq = (irq_pin + pci_extract_slot(device) - 2) % 4;
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uint32_t int_line = pci_read_field(device, PCI_INTERRUPT_LINE, 1);
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pr_default("Slot is %d, irq pin is %d, so pirq is %d and that maps to %d?"
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"int_line=%d\n",
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pci_extract_slot(device), irq_pin, pirq, pci_remaps[pirq],
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int_line);
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if (pci_remaps[pirq] == 0x80) {
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pr_default("Not mapped, remapping?\n");
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pci_remaps[pirq] = int_line;
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uint32_t out = 0;
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memcpy(&out, &pci_remaps, 4);
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pci_write_field(pci_isa, 0x60, 4, out);
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return pci_read_field(device, PCI_INTERRUPT_LINE, 1);
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}
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return pci_remaps[pirq];
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}
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static void __scan_count(uint32_t device, uint16_t vendorid, uint16_t deviceid, void *extra)
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{
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(void)device;
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(void)vendorid;
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(void)deviceid;
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size_t *count = extra;
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++(*count);
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}
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|
|
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static void __scan_hit_list(uint32_t device, uint16_t vendorid, uint16_t deviceid, void *extra)
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{
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(void)extra;
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pr_default("%2x:%2x.%d\n", pci_extract_bus(device), pci_extract_slot(device), pci_extract_func(device), deviceid);
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pr_default(" Vendor : [0x%06x] %s\n", vendorid, pci_vendor_lookup(vendorid));
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pr_default(" Device : [0x%06x] %s\n", deviceid, pci_device_lookup(vendorid, deviceid));
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pr_default(" Type : [0x%06x] %s\n", pci_find_type(device), pci_class_lookup(pci_find_type(device)));
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pr_default(" Status : 0x%4x\n", pci_read_field(device, PCI_STATUS, 2));
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pr_default(" Command : 0x%4x\n", pci_read_field(device, PCI_COMMAND, 2));
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pr_default(" Revision : %2d\n", pci_read_field(device, PCI_REVISION_ID, 1));
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pr_default(" Cache Line Size : %2d\n", pci_read_field(device, PCI_CACHE_LINE_SIZE, 1));
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pr_default(" Latency Timer : %2d\n", pci_read_field(device, PCI_LATENCY_TIMER, 1));
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pr_default(" Header Type : %2d\n", pci_read_field(device, PCI_HEADER_TYPE, 1));
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pr_default(" BIST : %2d\n", pci_read_field(device, PCI_BIST, 1));
|
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pr_default(" BAR0 : 0x%08x\n", pci_read_field(device, PCI_BASE_ADDRESS_0, 4));
|
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pr_default(" BAR1 : 0x%08x\n", pci_read_field(device, PCI_BASE_ADDRESS_1, 4));
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pr_default(" BAR2 : 0x%08x\n", pci_read_field(device, PCI_BASE_ADDRESS_2, 4));
|
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pr_default(" BAR3 : 0x%08x\n", pci_read_field(device, PCI_BASE_ADDRESS_3, 4));
|
|
pr_default(" BAR4 : 0x%08x\n", pci_read_field(device, PCI_BASE_ADDRESS_4, 4));
|
|
pr_default(" BAR6 : 0x%08x\n", pci_read_field(device, PCI_BASE_ADDRESS_5, 4));
|
|
pr_default(" Cardbus CIS : 0x%08x\n", pci_read_field(device, PCI_CARDBUS_CIS, 4));
|
|
pr_default(" Subsystem V. ID : 0x%08x\n", pci_read_field(device, PCI_SUBSYSTEM_VENDOR_ID, 2));
|
|
pr_default(" Subsystem ID : 0x%08x\n", pci_read_field(device, PCI_SUBSYSTEM_ID, 2));
|
|
pr_default(" ROM Base Address: 0x%08x\n", pci_read_field(device, PCI_ROM_ADDRESS, 4));
|
|
pr_default(" PCI Cp. LinkList: 0x%08x\n", pci_read_field(device, PCI_CAPABILITY_LIST, 1));
|
|
pr_default(" Max Latency : 0x%08x\n", pci_read_field(device, PCI_MAX_LAT, 1));
|
|
pr_default(" Min Grant : 0x%08x\n", pci_read_field(device, PCI_MIN_GNT, 1));
|
|
pr_default(" Interrupt Pin : %2d\n", pci_read_field(device, PCI_INTERRUPT_PIN, 1));
|
|
pr_default(" Interrupt Line : %2d\n", pci_read_field(device, PCI_INTERRUPT_LINE, 1));
|
|
pr_default(" Interrupt Number: %2d\n", pci_get_interrupt(device));
|
|
pr_default("\n");
|
|
}
|
|
|
|
void pci_debug_scan()
|
|
{
|
|
pr_default("\n--------------------------------------------------\n");
|
|
pr_default("Counting PCI entities...\n");
|
|
size_t count = 0;
|
|
pci_scan(&__scan_count, -1, &count);
|
|
pr_default("Total PCI entities: %d\n", count);
|
|
|
|
pr_default("Scanning PCI entities...\n");
|
|
pci_scan(&__scan_hit_list, -1, NULL);
|
|
|
|
pr_default("Mapping PCI entities...\n");
|
|
pci_remap();
|
|
|
|
pr_default("--------------------------------------------------\n");
|
|
}
|
|
|
|
///! @endcond
|