Enrico Fraccaroli (Galfurian)
326 lines
9.8 KiB
C
326 lines
9.8 KiB
C
/// @file proc_access.h
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/// @brief Set of functions and flags used to manage processors registers.
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/// @copyright (c) 2014-2023 This file is distributed under the MIT License.
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/// See LICENSE.md for details.
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#pragma once
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#include "stdint.h"
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#define CR0_PE 0x00000001u ///< Protected mode Enable.
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#define CR0_MP 0x00000002u ///< "Math" Present (e.g. npx), wait for it.
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#define CR0_EM 0x00000004u ///< EMulate NPX, e.g. trap, don't execute code.
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#define CR0_TS 0x00000008u ///< Process has done Task Switch, do NPX save.
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#define CR0_ET 0x00000010u ///< 32 bit (if set) vs 16 bit (387 vs 287).
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#define CR0_PG 0x80000000u ///< Paging Enable.
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#define CR4_SEE 0x00008000u ///< Secure Enclave Enable XXX.
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#define CR4_SMAP 0x00200000u ///< Supervisor-Mode Access Protect.
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#define CR4_SMEP 0x00100000u ///< Supervisor-Mode Execute Protect.
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#define CR4_OSXSAVE 0x00040000u ///< OS supports XSAVE.
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#define CR4_PCIDE 0x00020000u ///< PCID Enable.
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#define CR4_RDWRFSGS 0x00010000u ///< RDWRFSGS Enable.
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#define CR4_SMXE 0x00004000u ///< Enable SMX operation.
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#define CR4_VMXE 0x00002000u ///< Enable VMX operation.
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#define CR4_OSXMM 0x00000400u ///< SSE/SSE2 exception support in OS.
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#define CR4_OSFXS 0x00000200u ///< SSE/SSE2 OS supports FXSave.
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#define CR4_PCE 0x00000100u ///< Performance-Monitor Count Enable.
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#define CR4_PGE 0x00000080u ///< Page Global Enable.
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#define CR4_MCE 0x00000040u ///< Machine Check Exceptions.
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#define CR4_PAE 0x00000020u ///< Physical Address Extensions.
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#define CR4_PSE 0x00000010u ///< Page Size Extensions.
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#define CR4_DE 0x00000008u ///< Debugging Extensions.
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#define CR4_TSD 0x00000004u ///< Time Stamp Disable.
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#define CR4_PVI 0x00000002u ///< Protected-mode Virtual Interrupts.
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#define CR4_VME 0x00000001u ///< Virtual-8086 Mode Extensions.
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/// @brief Reads the Extra Segment (DS).
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/// @return the value we read.
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static inline uint16_t get_es(void)
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{
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uint16_t es;
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__asm__ __volatile__("mov %%es, %0"
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: "=r"(es));
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return es;
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}
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/// @brief Sets the Extra Segment (DS).
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/// @param es the value we set.
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static inline void set_es(uint16_t es)
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{
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__asm__ __volatile__("mov %0, %%es"
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:
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: "r"(es));
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}
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/// @brief Reads the Data Segment (DS).
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/// @return the value we read.
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static inline uint16_t get_ds(void)
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{
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uint16_t ds;
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__asm__ __volatile__("mov %%ds, %0"
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: "=r"(ds));
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return ds;
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}
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/// @brief Sets the Data Segment (DS).
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/// @param ds the value we set.
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static inline void set_ds(uint16_t ds)
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{
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__asm__ __volatile__("mov %0, %%ds"
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:
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: "r"(ds));
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}
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/// @brief Reads FS.
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/// @return the value we read.
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static inline uint16_t get_fs(void)
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{
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uint16_t fs;
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__asm__ __volatile__("mov %%fs, %0"
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: "=r"(fs));
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return fs;
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}
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/// @brief Sets FS.
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/// @param fs the value we set.
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static inline void set_fs(uint16_t fs)
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{
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__asm__ __volatile__("mov %0, %%fs"
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:
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: "r"(fs));
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}
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/// @brief Reads GS.
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/// @return the value we read.
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static inline uint16_t get_gs(void)
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{
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uint16_t gs;
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__asm__ __volatile__("mov %%gs, %0"
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: "=r"(gs));
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return gs;
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}
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/// @brief Sets GS.
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/// @param gs the value we set.
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static inline void set_gs(uint16_t gs)
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{
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__asm__ __volatile__("mov %0, %%gs"
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:
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: "r"(gs));
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}
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/// @brief Reads the Stack Segment (SS).
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/// @return the value we read.
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static inline uint16_t get_ss(void)
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{
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uint16_t ss;
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__asm__ __volatile__("mov %%ss, %0"
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: "=r"(ss));
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return ss;
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}
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/// @brief Sets the Stack Segment (SS).
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/// @param ss the value we set.
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static inline void set_ss(uint16_t ss)
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{
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__asm__ __volatile__("mov %0, %%ss"
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:
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: "r"(ss));
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}
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/// @brief Reads the current cr0 value.
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/// @return the value we read.
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static inline uintptr_t get_cr0(void)
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{
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uintptr_t cr0;
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__asm__ __volatile__("mov %%cr0, %0"
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: "=r"(cr0));
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return (cr0);
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}
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/// @brief Sets the cr0 value.
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/// @param cr0 the value we want to set.
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static inline void set_cr0(uintptr_t cr0)
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{
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__asm__ __volatile__("mov %0, %%cr0"
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:
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: "r"(cr0));
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}
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/// @brief Reads the current cr3 value.
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/// @return the value we read.
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static inline uintptr_t get_cr3(void)
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{
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uintptr_t cr3;
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__asm__ __volatile__("mov %%cr3, %0"
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: "=r"(cr3));
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return (cr3);
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}
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/// @brief Sets the cr3 value.
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/// @param cr3 the value we want to set.
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static inline void set_cr3(uintptr_t cr3)
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{
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__asm__ __volatile__("mov %0, %%cr3"
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:
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: "r"(cr3));
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}
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/// @brief Reads the current cr4 value.
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/// @return the value we read.
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static inline uintptr_t get_cr4(void)
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{
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uintptr_t cr4;
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__asm__ __volatile__("mov %%cr4, %0"
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: "=r"(cr4));
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return (cr4);
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}
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/// @brief Sets the cr4 value.
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/// @param cr4 the value we want to set.
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static inline void set_cr4(uintptr_t cr4)
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{
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__asm__ __volatile__("mov %0, %%cr4"
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:
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: "r"(cr4)
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: "memory");
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}
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/// @brief Reads entire contents of the EFLAGS register.
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/// @return the content of EFLAGS.
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static inline uintptr_t get_eflags(void)
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{
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uintptr_t eflags;
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// "=rm" is safe here, because "pop" adjusts the stack before
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// it evaluates its effective address -- this is part of the
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// documented behavior of the "pop" instruction.
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__asm__ __volatile__("pushf; pop %0"
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: "=rm"(eflags)
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: // no input
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: "memory");
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return eflags;
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}
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/// @brief Clears the task-switched (TS) flag in the CR0 register.
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static inline void clear_ts(void)
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{
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__asm__ __volatile__("clts");
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}
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/// @brief Reads the segment selector from the task register (TR).
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/// @return
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static inline unsigned short get_tr(void)
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{
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unsigned short seg;
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__asm__ __volatile__("str %0"
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: "=rm"(seg));
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return (seg);
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}
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/// @brief Loads the source operand into the segment selector field of the task register.
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/// @param seg the segment selector we want to set.
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static inline void set_tr(unsigned short seg)
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{
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__asm__ __volatile__("ltr %0"
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:
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: "rm"(seg));
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}
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/// @brief Reads the segment selector from the local descriptor table register (LDTR).
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/// @return the segment selector.
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static inline unsigned short sldt(void)
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{
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unsigned short seg;
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__asm__ __volatile__("sldt %0"
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: "=rm"(seg));
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return (seg);
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}
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/// @brief Loads the source operand into the segment selector field of the local descriptor table register (LDTR).
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/// @param seg The segment selector we need to set.
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static inline void lldt(unsigned short seg)
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{
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__asm__ __volatile__("lldt %0"
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:
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: "rm"(seg));
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}
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/// @brief Loads the values in the source operand into the global descriptor
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/// table register (GDTR) or the interrupt descriptor table register (IDTR).
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/// @param desc the value we need to load.
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static inline void lgdt(uintptr_t *desc)
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{
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__asm__ __volatile__("lgdt %0"
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:
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: "m"(*desc));
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}
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/// @brief Loads the values in the source operand into the global descriptor
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/// table register (GDTR) or the interrupt descriptor table register (IDTR).
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/// @param desc the value we need to load.
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static inline void lidt(uintptr_t *desc)
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{
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__asm__ __volatile__("lidt %0"
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:
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: "m"(*desc));
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}
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/// @brief Set interrupt flag; external, maskable interrupts enabled at the end
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/// of the next instruction.
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static inline void sti(void)
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{
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__asm__ __volatile__("sti"
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:
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:
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: "memory");
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}
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/// @brief Clear interrupt flag; interrupts disabled when interrupt flag
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/// cleared.
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static inline void cli(void)
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{
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__asm__ __volatile__("cli"
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:
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:
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: "memory");
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}
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/// @brief Exchanges the current GS base register value with the value contained
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/// in MSR address C0000102H.
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static inline void swapgs(void)
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{
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__asm__ __volatile__("swapgs");
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}
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/// @brief Halts the CPU until the next external interrupt is fired.
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static inline void hlt(void)
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{
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__asm__ __volatile__("hlt");
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}
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/// @brief Gives hint to processor that improves performance of spin-wait loops.
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static inline void pause(void)
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{
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__asm__ __volatile__("pause");
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}
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// == Memory clobbers =========================================================
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// Memory clobber implies a fence, and it also impacts how the compiler treats
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// potential data aliases. A memory clobber says that the asm block modifies
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// memory that is not otherwise mentioned in the asm instructions.
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// So, for example, a correct use of memory clobbers would be when using an
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// instruction that clears a cache line. The compiler will assume that
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// virtually any data may be aliased with the memory changed by that
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// instruction. As a result, all required data used after the asm block
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// will be reloaded from memory after the asm completes. This is much more
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// expensive than the simple fence implied by the "volatile" attribute.
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// == Volatile Block ==========================================================
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// Making an inline asm block "volatile" as in this example, ensures that,
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// as it optimizes, the compiler does not move any instructions above or
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// below the block of asm statements.
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// __asm__ __volatile__(" addic. %0,%1,%2\n" : "=r"(res): "=r"(a),"r"(a))
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// This can be particularly important in cases when the code is accessing
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// shared memory.
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